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M68Z512W
4 Mbit (512 Kbit x 8) LOW VOLTAGE, LOW POWER SRAM WITH OUTPUT ENABLE
FEATURES SUMMARY s ULTRA LOW DATA RETENTION CURRENT - 400nA (typical) - 10A (max)
s s s s s s s
Figure 1. 32-pin TSOP Package
OPERATION VOLTAGE: 2.7 TO 3.6V 512 Kbit x 8 SRAM WITH OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 70ns LOW VCC DATA RETENTION: 1V TRI-STATE COMMON I/O CMOS FOR OPTIMUM SPEED/POWER AUTOMATIC POWER-DOWN WHEN DESELECTED INTENDED FOR USE WITH ST ZEROPOWER(R) AND TIMEKEEPER(R) SUPERVISORS
1
TSOP II 32 (NC) 10 x 20mm
32
s
May 2002
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M68Z512W
TABLE OF CONTENTS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Logic Diagram (Figure 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Signal Names (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 TSOP Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block Diagram (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC and AC Measurement Conditions (Table 3.) . . . AC Testing Load Circuit (Figure 5.) . . . . . . . . . . . . . Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... .....5 .....5 .....5 .....6
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operating Modes (Table 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 READ Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Address Controlled, READ Mode AC Waveforms (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chip Enable or Output Enable Controlled, READ Mode AC Waveforms (Figure 7.). . . . . . . . . . . . . 7 READ Mode AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WRITE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write Enable Controlled, WRITE Mode AC Waveforms (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip Enable Controlled, WRITE Mode AC Waveforms (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . 9 WRITE Mode AC Characteristics (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Low VCC Data Retention AC Waveforms (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Low VCC Data Retention Characteristics (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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M68Z512W
DESCRIPTION The M68Z512W is a 4Mbit (4,194,304 bit) CMOS SRAM, organized as 524,288 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 3V 10% supply, and all inputs and outputs are TTL compatible.
This device has an automatic power-down feature, reducing the power consumption by over 99% when deselected. The M68Z512W is available in a 32-lead TSOP II (10 x 20mm) package.
Figure 2. Logic Diagram
VCC
Table 1. Signal Names
A0-A18 DQ0-DQ7 Address Inputs Data Input/Output Chip Enable Output Enable Write Enable Supply Voltage Ground
19 A0-A18
8 DQ0-DQ7
E G W
W E
M68Z512W
VCC VSS
G
VSS
AI03072
Figure 3. TSOP Connections
A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 32 VCC A15 A18 W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
8 9
M68Z512W
25 24
16
17
AI03073
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M68Z512W
Figure 4. Block Diagram
A (10) A CHIP ENABLE. DQ (8) DQ INPUT DATA CTRL I/O CIRCUITS COLUMN DECODER ROW DECODER MEMORY ARRAY VCC VSS
CHIP ENABLE. (9) A E W A
G
AI03033
MAXIMUM RATING Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 2. Absolute Maximum Ratings
Symbol TA TSTG(1) VIO(2) VCC IO(3) PD Parameter Ambient Operating Temperature Storage Temperature Input or Output Voltage Supply Voltage Output Current Power Dissipation
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Value 0 to 70 -65 to 150 -0.3 to VCC + 0.3 -0.3 to 4.6 20 1
Unit C C V V mA W
Note: 1. Reflow at peak temperature of 215C to 225C for < 60 seconds (total thermal budget not to exceed 180C for between 90 and 120 seconds). 2. Up to a maximum operating VCC of 3.6V only. 3. One output at a time, not to exceed 1 second duration.
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M68Z512W
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the MeasureTable 3. DC and AC Measurement Conditions
Parameter VCC Supply Voltage Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages M68Z512W 2.7 to 3.6V 0 to 70C 30pF 5ns 0 to 3V 1.5V
ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Figure 5. AC Testing Load Circuit
3.0V
1105 DEVICE UNDER TEST 1550
OUT
CL = 30pF or 5pF
CL includes JIG capacitance
AI03074
Table 4. Capacitance
Symbol CIN COUT(3) Parameter(1,2) Input Capacitance on all pins (except DQ) Output Capacitance Min Max 6 8 Unit pF pF
Note: 1. Effective capacitance measured with power supply at 3V; sampled only, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs deselected.
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M68Z512W
Table 5. DC Characteristics
Symbol ILI ILO ICC1(2) ICC2(3) ICC3(4) VIL VIH VOL VOH
Note: 1. 2. 3. 4.
Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Test Condition(1) 0V VIN VCC 0V VOUT VCC VCC = 3.6V VCC = 3.6V, E = VIH VCC = 3.6V, E VCC - 0.3V, f = 0
Min
Typ
Max 1 1
Unit A A mA A A V V V V
7
15 100
2 -0.3 2.2
20 0.8 VCC + 0.3 0.4
IOL = 2.1mA IOH = -1mA 2.4
Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 2.7 to 3.6V (except where noted). Average AC current, Outputs open, cycling at t AVAV minimum. All other Inputs at VIL 0.8V or VIH 2.2V. All other Inputs at VIL 0.3V or VIH VCC -0.3V.
OPERATION The M68Z512W has a Chip Enable power down feature which invokes an automatic standby mode whenever Chip Enable is de-asserted (E = High). An Output Enable (G) signal provides a high speed tri-state control, allowing fast READ/WRITE Table 6. Operating Modes
Operation Read Read Write Deselect
Note: X = VIH or VIL.
Cycles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs W and E as summarized in the Operating Modes table (see Table 6).
E VIL VIL VIL VIH
W VIH VIH VIL X
G VIH VIL X X
DQ0-DQ7 Hi-Z Data Output Data Input Hi-Z
Power Active Active Active Standby
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M68Z512W
READ Mode The M68Z512W is in the READ Mode whenever WRITE Enable (W) is High with Output Enable (G) Low, and Chip Enable (E) is asserted. This provides access to data from eight of the 4,194,304 locations in the static memory array, specified by the 19 address inputs. Valid data will be available at the eight output pins within tAVQV after the last
stable address, providing G is Low and E is Low. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tELQV or tGLQV) rather than the address. Data out may be indeterminate at tELQX and tGLQX, but data lines will always be valid at tAVQV.
Figure 6. Address Controlled, READ Mode AC Waveforms
tAVAV A0-A18 tAVQV VALID tAXQX
DQ0-DQ7
DATA VALID
AI03034
Note: E = Low, G = Low, W = High.
Figure 7. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms
tAVAV A0-A18 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 VALID
AI03035
VALID tAXQX tEHQZ
tGHQZ
Note: Write Enable (W) = High.
Figure 8. Standby Mode AC Waveforms
E ICC1 ICC2 tPU 50% tPD
AI03036
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M68Z512W
Table 7. READ Mode AC Characteristics
Symbol tAVAV tAVQV tELQV tGLQV tELQX(3) tGLQX(3) tEHQZ
(2,3)
Parameter(1) READ Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition Chip Enable Low to Power Up Chip Enable High to Power Down
M68Z512W Min 70 70 70 35 10 5 25 25 10 0 70 Max
Unit ns ns ns ns ns ns ns ns ns ns ns
tGHQZ(2,3) tAXQX tPU tPD
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 2.7 to 3.6V (except where noted). 2. CL = 5pF. 3. At any given temperature and voltage condition, t EHQZ is less than tELQX and tGHQZ is less than tGLQX for any given device.
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M68Z512W
WRITE Mode The M68Z512W is in the WRITE mode whenever the W and E pins are Low. Either the Chip Enable input (E) or the WRITE Enable input (W) must be de-asserted during Address transitions for subsequent WRITE cycles. Write begins with the concurrence of Chip Enable being active with W low. Therefore, address setup time is referenced to WRITE Enable and Chip Enable as tAVWL and tAVEH respectively, and is determined by the latter occurring edge.
The WRITE Cycle can be terminated by the earlier rising edge of E, or W. If the Output is enabled (E = Low and G = Low), then W will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of WRITE Enable, or for tDVEH before the rising edge of E, whichever occurs first, and remain valid for tWHDX or tEHDX.
Figure 9. Write Enable Controlled, WRITE Mode AC Waveforms
tAVAV A0-A18 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI03037
tWHAX
tWHQX
Note: Output Enable (G) = Low.
Figure 10. Chip Enable Controlled, WRITE Mode AC Waveforms
tAVAV A0-A18 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI03038
tELEH
tEHAX
Note: If E goes High with W High, the output remains in a high-impedance state, and Output Enable (G) = Low
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M68Z512W
Table 8. WRITE Mode AC Characteristics
Symbol tAVAV tAVWL tAVWH tAVEH tWLWH tWHAX tWHDX tWHQX(3) tWLQZ(2,3) tAVEL tELEH tEHAX tDVWH tDVEH WRITE Cycle Time Address Valid to WRITE Enable Low Address Valid to WRITE Enable High Address Valid to Chip Enable High WRITE Enable Pulse Width WRITE Enable High to Address Transition WRITE Enable High to Input Transition WRITE Enable High to Output Transition WRITE Enable Low to Output Hi-Z Address Valid to Chip Enable Low Chip Enable Low to Chip Enable High Chip Enable High to Address Transition Input Valid to Write Enable High Input Valid to Chip Enable High 0 60 0 30 30 Parameter(1) M68Z512W Unit Min 70 0 60 60 50 0 0 5 25 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 2.7 to 3.6V (except where noted). 2. CL = 5pF 3. At any given temperature and voltage condition, t WLQZ is less than tWHQX for any given device.
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M68Z512W
Figure 11. Low VCC Data Retention AC Waveforms
DATA RETENTION MODE VCC VDR VDR > 1.0V tCDR E VDR - 0.3V E 2.2V tER
AI03039
Table 9. Low VCC Data Retention Characteristics
Symbol ICCDR
(2)
Parameter(1) Supply Current (Data Retention) Supply Voltage (Data Retention) Chip Disable to Power Down Operation Recovery Time
Test Condition VCC = 3V, E VCC - 0.3V E VCC - 0.3V, f = 0 E VCC - 0.3V, f = 0
Min
Typ 0.4
Max 10
Unit A V ns ns
VDR tCDR tER
(3,4)
1 0 tAVAV
Note: 1. 2. 3. 4.
Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 2.7 to 3.6V (except where noted). Typical condition: T A = 25C. See Figure 11 for measurement points. Guaranteed but not tested. tAVAV is READ Cycle time. Full device AC operation requires linear VCC ramp from VDR to VCC (min) 10s or stable at VCC (min) 10s.
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M68Z512W
PART NUMBERING Table 10. Ordering Information Example
Example: M68Z 512 W -70 NC 1
Device Type M68Z
Device Function 512 = 4 Mbit (512Kb x8)
Operating Voltage W = 2.7 to 3.6V
Speed -70 = 70ns
Package NC = TSOP II 32-Lead (10 x 20mm)
Temperature Range 1 = 0 to 70C
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M68Z512W
PACKAGE MECHANICAL INFORMATION Figure 12. TSOP II 32 - 32-lead Plastic Thin Small Outline II, 10 x 20 mm, Package Outline
D
16
1
E1
E
17
32
b
e
A
A2 C A1 CP L
TSOP-d
Note: Drawing is not to scale.
Table 11. TSOP II 32 - 32-lead Plastic Thin Small Outline II, 10 x 20 mm, Package Mechanical Data
mm Symb Min A A1 A2 b C CP D e E E1 L N 1.27 20.82 - 11.56 10.03 0.40 0 32 0.05 0.95 0.30 0.12 Typ Max 1.20 0.15 1.05 0.52 0.21 0.10 21.08 - 11.96 10.29 0.60 5 0.050 0.820 - 0.455 0.395 0.016 0 32 0.002 0.037 0.012 0.005 Min Typ Max 0.047 0.006 0.041 0.020 0.008 0.004 0.830 - 0.471 0.405 0.024 5 inches
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M68Z512W
REVISION HISTORY Table 12. Document Revision History
Date July 1999 06/28/00 07/26/00 09/21/00 06/07/01 07/23/01 05/13/02 First Issue TSOP32 II Package Dimension Changed (Table 11) From Target Specification To Preliminary Data Ordering Information Scheme changed (Table 10) ICCDR Supply Current changed (Table 9) Reformatted; temp./voltage info. added to tables (Table 4, 5, 7, 8, 9); product status change Routine maintenance (based on recent data sheet review findings) Add reflow time and temperature footnote (Table 2) Revision Details
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M68Z512W
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com
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